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AILED
safety board

Designed the accumulator's high-voltage indicator board from schematic through PCB layout. Powered straight from the 588 V tractive bus, with no GLV or software dependency, including with the pack disconnected.

  1. Requirements
  2. Architecture
  3. Schematic
  4. PCB layout
Overhead render of the AILED board Marco designed: the fuse, film capacitors and flyback transformer on the HV side, the indicator circuit on the LV side, and the isolation barrier between them
Three parts cross the isolation barrier1INN3996CQ switcher2Flyback transformer3CNY65 optocoupler
588 VTractive bus
57.4 VTrip point, nominal
12.7 mmCreepage, DRC clean
NoneSoftware in the loop
Why it matters

Five rules, each answered in hardware.

The AILED is a rules-required safety light: whenever the accumulator's bus is live, it has to say so, even when everything else on the car is off.

RuleRequiresThe board
EV.5.7

Indicate high voltage at the vehicle side of the isolation relays.

A TLV3011 comparator on the bus trips at 57.4 V nominal.

EV.5.7.1

Keep working with the pack disconnected or removed.

Powered from the bus itself: the isolated flyback starts at about 35 V.

EV.5.7.2

HV presence directly powers and controls it, hard-wired, no software.

Analog end to end: divider, comparator, optocoupler. No firmware anywhere.

EV.5.7.3

The isolation relay control signal must not control it.

Nothing on the detection path connects to the relay control signal.

EV.6.5.7

Keep HV and LV apart on the board.

Designed around 12.7 mm creepage and 9.5 mm clearance across the isolation barrier.

Architecture

Two paths across one barrier.

AILED architectureBlock diagram: the HV bus at the vehicle side of the isolation relays, up to 588 volts, feeds an isolated flyback converter built around the INN3996CQ, which starts at about 35 volts and crosses the isolation barrier to produce a 12 volt rail and an auxiliary 5 volt output for the BMU 555 timer that flashes the ready-to-move light. A separate comparator senses the HV bus and enables the 12 volt indicator output above 57.4 volts nominal; it does not control the flyback controller.HV REGIONISOLATED LV REGIONISOLATION BARRIERCREEPAGE + CLEARANCEHV bus≤ 588 VIR vehicle side57.4 VcomparatorIsolatedflybackINN3996CQstarts ≈ 35 V5 V auxto BMU555 timer · RTML12 Vgate12 VAILED outsteady blue LEDenable above 57.4 Vhard-wiredno softwareworks with packdisconnectedno LV supplyrequired

Flyback up from ~35 V · comparator enables the steady 12 V indicator above 57.4 V · 5 V aux to the BMU timer

PCB layout · Altium

The barrier, cut into the board.

2Copper layers
109 × 86 mmBoard outline
3 × 5 mmMilled isolation slots
0DRC violations, 18 rules
PCB layout of the AILED board, drawn from its Gerber files: top and bottom copper, silkscreen, and three milled slots in a line along the isolation barrier, one under each part that crosses it
Milled slots under the crossings1U1 INN3996CQ switcher2X1 Flyback transformer3U3 CNY65 optocoupler
  1. 01

    Creepage as a design rule

    Altium checks 12.7 mm along the board surface and 9.5 mm through air between the HV_DOMAIN and LV_DOMAIN net classes. Both pass with zero violations.

  2. 02

    A slot under every crossing

    Each part that bridges the barrier sits over a 5 mm milled slot: 15 mm under U1, 30 mm under the transformer, 17 mm under U3. Together they cut 62 of the 86 mm along the barrier.

  3. 03

    Clean at handoff

    A separate 4 mm rule keeps the tractive bus nets away from HV ground, and all 18 rules, from 0.2 mm trace width to silkscreen clearance, report zero violations.

Sheet 1 of 3 · Power path

The isolated flyback.

12 VRegulated output
0.3 ASecondary current limit
1200 VSiC clamp diode
1.07 MΩBus sense network
TS+ HV_GND HV_GND IS 1 GND 2 FB 3 BPS 4 SR 5 VOUT 6 FWD 7 NC 8 NC 9 NC 10 NC 11 NC 12 V 13 BPP 14 NC 15 S 16 S 17 S 18 S 19 D 24 U1 INN3996CQ HV_GND 470nF C6 SEC_GND 2.2uF C5 12V_ISO_RAW 84.5KR R3 12V_ISO_RAW 10KR R4 220 pF C4 0.12 Ohm R1 SEC_GND GND 267k R5 267k R6 267k R7 267k R8 TS+ 210k R9 HV_GND * DDZ9696-7 PRI_1 1 NC_1 2 PRI_2 3 NC_2 4 AUX_1 5 AUX_2 6 NC_3 7 SEC_1 8 SEC_2 9 SEC_3 10 SEC_4 11 NC_4 12 X1 ZD2200-BE SEC_SW 12V_ISO_RAW D2 STPS2150A 100 R10 CRCW0603100RFKEA SEC_SW 1 2 + 100uF C2 25SVPF100M D3 S1G-13-F 1 2 + 47 uF C3 EEH-ZC1H470P 1 2 5.1kR R2 CRCW12065K10FKEA AUX_BIAS 2 uF C1 1 3 2 CR2 STPSC2H12B2Y-TR TVS CR1 5.0SMDJ150A PRI_CLAMP 12V_ISO_RAW 2 1 D1 SS34-E3/57T GND AUX_BIAS Two sec coils in parallel
Power path sheet · INN3996CQ controller, ZD2200 transformer · completed schematic
  1. 01

    Output set by feedback

    The 84.5k / 10k divider on the controller's 1.265 V feedback reference sets 11.95 V.

  2. 02

    Current limited on the secondary

    About 36 mV across the 0.12 Ω sense resistor trips the limit near 0.3 A.

  3. 03

    Drain spikes clamped

    Leakage spikes route through a 1200 V SiC diode into a 150 V TVS above the bus.

Marco's handwritten notes on the flyback: the INN3996CQ's primary and secondary sides drawn around the ZD2200 transformer, annotated with start-up and turn-off voltages, the bypass supply, OV protection and the 1.265 V feedback reference
From my notebook · Working out the INN3996CQ before drawing the schematic
Sheet 2 of 3 · Comparator

Detecting the bus, across the barrier.

57.4 VTrip point, nominal
1.242 VComparator reference
46.2 : 1Bus divider
5 VHV-side rail
AUX_BIAS TS+ HV_GND HV_GND OUT 1 NC_1 2 DELAY 3 NC_2 4 EP 9 IN 8 NC_3 7 PG 6 GND 5 B2 TPS7B8750QDDARQ1 HV_GND 5V_HV 1uF C9 UMK107AB7105KA-T 4.7uF C10 GRM21BR71C475KE51L OUT 1 V- 2 IN+ 3 V+ 6 REF 5 IN- 4 B1 TLV3011BIDBVR HV_GND 0.10 µF C7 C0603C104K5RACTU 20KR R16 RT0402BRB0720KL HV_GND 226k R11 RQ73C2B226KBTD 226k R12 RQ73C2B226KBTD 226k R13 RQ73C2B226KBTD 226k R14 RQ73C2B226KBTD ANODE_1 1 ANODE_2 2 COMMON_CATHODE 3 D4 BAV170_215 10kR R15 RMCF0402FT10K0 2.2kO R17 ERJ-2RKF2201X 2.2kO R20 ERJ-2RKF2201X 10nF C8 GCM155R71H103KA55D HV_GND HV_GND IN_CLAMP ANODE 1 CATHODE 2 EMITTER 3 COLLECTOR 4 U3 CNY65AGRST BASE 1 EMITTER 2 COLLECTOR 3 U2 BC857B 4.7kOhms R18 RC0603FR-074K7L 5V_HV 100K R19 RC0402FR-07100KL 470 Ohm R21 RC0402FR-07470RL HV_GND AILED_GATE_CTRL 12V_ISO_RAW
Comparator sheet · TLV3011 comparator, CNY65 optocoupler · completed schematic
  1. 01

    Threshold from the reference

    Four 226k resistors over 20k divide the bus by 46.2, so the TLV3011 trips against its internal 1.242 V reference at 57.38 V, leaving margin below 60 V for offset and hysteresis.

  2. 02

    Light holds the indicator off

    Below the threshold the comparator keeps a BC857 PNP on, lighting a CNY65 optocoupler that pulls the isolated gate line up to 12 V. Above 57.4 V the light goes out and the indicator turns on.

  3. 03

    Powered from the flyback

    A TPS7B87 LDO makes the 5 V HV-side rail from the flyback's auxiliary bias, and a BAV170 diode pair on IN_CLAMP protects the comparator input.

Sheet 3 of 3 · LV logic

An indicator that fails lit.

12 VIndicator output
P-FETHigh-side switch
5 VBMU timer rail
LitFail-safe state
GND GND 12V_ISO_RAW 3 1 2 Q1 DMP3098L-7 47kR R22 RC0603FR-0747KL GND 330 Ohm R24 RC0603FR-07330RL AILED_GATE_CTRL 12V_AILED OUT 1 NC_1 2 DELAY 3 NC_2 4 EP 9 IN 8 NC_3 7 PG 6 GND 5 B3 TPS7B8750QDDARQ1 GND 5V_555_OUT 2 1 D5 APT1608LZGCK 10kR R23 RC0603FR-0710KL GND 1uF C11 UMK107AB7105KA-T 4.7uF C12 GRM21BR71C475KE51L Gate pull-down 12V rail status indicator
LV logic sheet · DMP3098L high-side switch, TPS7B87 LDO · completed schematic
  1. 01

    High-side P-FET switch

    Q1, a DMP3098L, switches the isolated 12 V rail onto the indicator connector. R22 pulls its gate low, so it conducts unless the optocoupler pulls the gate up.

  2. 02

    Fails toward lit

    The HV side has to actively hold the indicator off. Losing the HV-side 5 V rail or the optocoupler's LED leaves it lit, the safe direction for a high-voltage warning.

  3. 03

    5 V for the BMU timer

    A TPS7B87 LDO makes 5 V for the BMU's 555 RTML timer from the same isolated rail, and a green LED shows the 12 V rail is up.

Completed design

From requirements to PCB.

Completed the architecture, all three schematic sheets, and a DRC-clean PCB layout in Altium. The board render shows the finished design, from the HV power path and isolation barrier to the LV indicator circuitry.